Mahmudi, Ali (2018) Modified Welch Berlekamp Algorithm to Decode Reed Solomon Codes. In: MATEC Web of Conferences 164, 01003 (2018, ICESTI 2017. (Submitted)
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Modified Welch Berlekamp Algorithm to Decode Reed Solomon Codes Ali - TURNITIN.pdf Available under License Creative Commons Attribution Non-commercial Share Alike. Download (1MB) |
Abstract
In this paper, the Reed Solomon Code is decoded using the Welch-Berlekamp Algorithm. The RS Decoder is implemented using Hardware Description Language VHDL (VHSIC hardware Description Language) and simulated on Modelsim software. Some modifications have been carried out on the Welch Berlekamp algorithm in such a way that it is easier to implement. A pilot design double error correction RS(63, 59) decoder has been written in VHDL and simulated. The XILINX FPGA layout RS(63, 59) is then obtained.
| Item Type: | Conference or Workshop Item (Paper) |
|---|---|
| Uncontrolled Keywords: | FPGA, hard decision decoding, Reed Solomon Code, Welch Berlekamp algorithm |
| Subjects: | Engineering > Informatics Engineering |
| Divisions: | Fakultas Teknologi Industri > Teknik Informatika S1 |
| Depositing User: | Mrs Retno Wulan Sari |
| Date Deposited: | 24 Aug 2023 07:08 |
| Last Modified: | 24 Aug 2023 07:08 |
| URI: | http://eprints.itn.ac.id/id/eprint/12684 |
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